Semiconductor device technology is increasingly relying on specialty Si-based substrates to improve the performance of complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs). For example, the strong dependence of carrier mobility on silicon orientation has led to increased interest in hybrid orientation Si substrates in which nFETs are formed in (100)-oriented Si (the orientation in which electron mobility is higher) and pFETs are formed in (110)-oriented Si (the orientation in which hole mobility is higher), as described, for example, by M. Yang, et al. “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” IEDM 2003 Paper 18.7 and U.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003 entitled “High-performance CMOS SOI devices on hybrid crystal-oriented substrates”.
Amorphization/templated recrystallization (ATR) methods for fabricating hybrid orientation substrates (see, for example, U.S. patent application Ser. No. 10/725,850, filed Dec. 2, 2003 entitled “Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers”) typically start with a first semiconductor layer having a first orientation bonded to a second semiconductor layer having a second orientation different from the first. Selected areas of the first semiconductor layer are amorphized by ion implantation, and then recrystallized into the orientation of the second semiconductor layer using the second semiconductor layer as a crystal template.
FIG. 1 shows an ATR method for producing a hybrid orientation Si substrate, which utilizes top amorphization and bottom templating (i.e., the first semiconductor layer being amorphized is on the top and the second semiconductor layer acting as a template is on the bottom). FIG. 1A shows starting substrate 10 comprising bottom silicon substrate layer 20 having a bottom crystal orientation, top silicon substrate layer 30 having a different crystal orientation, and bonded interface 40 between them. Selected regions of top Si substrate layer 30 are then subjected to amorphizing ion implantation 50 to produce one or more amorphized regions 60 and non-amorphized top substrate regions 30′, as shown in FIG. 1B. Amorphized regions 60 span the entire thickness of the upper Si layer, and extend into lower Si layer 20. Amorphized regions 60 are then recrystallized into the bottom crystal orientation, using lower Si layer 20 as a template, to produce planar hybrid orientation substrate 70 with recrystallized, changed-orientation Si regions 80.
Traces of the damage produced by the amorphizing implant typically remain after recrystallization. For the FIG. 1 case of Si with top amorphization and bottom templating, the amorphizing implant will typically produce an “end-of-range” damage layer of highly defective crystalline Si in the template layer. This crystalline damage layer is bounded on the top by fully amorphized Si, and bounded on the bottom by the undamaged template. The damage layer interferes with the clean recrystallization of the amorphized Si, both by introducing threading defects (which can propagate to the wafer's surface) and by leaving a band of dislocation loops at the approximate position of the original damage layer. This is shown schematically in FIG. 2 for a non-patterned ATR process.
FIG. 2A shows a starting substrate structure 100, analogous to starting substrate structure 10 of FIG. 1A. FIG. 2A shows characteristic end-of-range damage layer 110 between bottom Si substrate layer 20 and amorphized layer 120 resulting from amorphizing ion implant 130. FIG. 2C shows the structure of FIG. 2B after amorphized layer 120 has recrystallized into crystalline layer 140 having the orientation of bottom silicon substrate layer 20. A layer of dislocation loops 150 has replaced damage layer 110. Threading defects 160 typically extend from some of the dislocation loops in layer 150 to the sample surface.
There is a vast literature on the subject of ion-implant induced defects and how to reduce and/or remove them, in large part because ion-implanted junctions are so critical to semiconductor device technology. For example, T. E. Seidel, in “Rapid Thermal Processing (RTP) of Shallow Silicon Junctions,” Mat. Res. Soc. Symp. Proc. 45 7 (1985), has discussed defect removal as a function of temperature for temperatures up to 1200° C. for Si samples implanted with 100 keV As at a dose of 5e15/cm2. In another reference, C. M. Hasenack et al., in “The suppression of residual defects of silicon implanted with group III, IV and V elements,” Semicond. Sci. Technol. 2 477 (1987), describe data suggesting that diffusion of the implanted dopants through the damage layer plays a helpful role in defect repair.
It is claimed in the prior art (e.g. T. E. Seidel, above) that end-of-range defects can be removed from I/I-amorphized 100-oriented Si by furnace or RTA annealing at temperatures <1200° C. However, this work is for cases in which diffusing dopants are present to assist in defect removal. In addition, because the focus of the prior work was on dopant activation rather than defect removal, the maximum annealing temperatures and times were constrained by the need to minimize dopant diffusion. Implant annealing at temperatures above 1200° C. has previously been taught only for the very short times (e.g., <1 sec) of laser annealing. However these short times are not optimal for defect removal in the absence of dopants (e.g., when amorphization is effected by implantation of Si+ or Ge+).
In view of the above, it would be highly desirable to have a method for repairing ion-implant-induced damage in ATR'd Si in cases for which (i) there are no implanted dopants to assist with the defect removal (e.g., the amorphization is effected with implantation of ions such as Si+ or Ge+), and (ii) the defect removal anneals are part of a process to change the Si crystal orientation. In addition it would be desirable to have a method that can work for Si orientations such as 110 (or 111), which (relative to Si 100) typically have both a higher starting defect density, and defects that are more stable and harder to remove.
More generally, it would also be desirable to have a method for amorphizing and recrystallizing selected semiconductor regions (into their original orientation or a different orientation) without introducing a large density of defects.